Job Details:Job Description: Advanced Design Group under Design Enablement in Technology Development has primary focus of Design-Technology Co-optimization (DTCO) and Foundational IP development to support both the Technology Development organization and Intel's IP/Product design teams. Advanced power, performance, and area (PPA) analyses are conducted across domains to guide Technology Development's research, pathfinding, and technology definition.

Library Technology Group in Advanced Design is looking for a highly motivated and experienced individual to lead the library development, and optimization of standard cell libraries to enable best-in-class IP and product design on all generations of Intel technology.Responsibilities include but are not limited to the following:As a technical lead, you are responsible for leading the standard cell development and optimization activities with active collaboration with process technologists, product design and IFS stake holders, and EDA vendors to achieve best-in-class cell/block level PPA and competitive EoU (Ease of Use) through DTCO (Design-Technology Co-Optimization)Assume leadership role managing small group of engineers in layout design development and pathfinding execution activities, driving automation and standardization in layout generation and migration capabilities.Supporting development and delivery for various process and PDK (process design kits) test-chips and benchmarking standard cells content.

Support Planning, Si validation learning to enhance standard cells yield, Vmin and power/performance.Required skills/experience:10+ years of experience working on digital logic design, standard cells benchmarking and test chip development, (foundational IP development and execution in DTCO, silicon implementation, or technology development) in advanced nodes.Preferred skills/experience:Strong track record and experience in leading std cell library development and definition to optimize PPA through DTCO on advanced technology nodes strongly preferred.

Experience managing small team of technical individual contributor.Bring external foundry best known methods to execution efficiency, library architecture DTCO and robust process design rules definition.Experience in EDA tool/flow/methodology, product, and IP developments, programming experience.

In-depth knowledge in digital design including CMOS combinatorial logic and sequential circuit and layout, and familiarity with design tradeoffs as well as standard cell modeling, extraction, and characterization highly desired.Familiar with foundry ecosystem and benchmarking practiceExcellent communication and interpersonal skills to champion initiatives internally and externally and drive effective communication with executive management and external partners.Technical, analytical, customer oriented and cross-functional collaboration skillsAbility to work in a dynamic and matrix team-oriented environment.

Strong independence and proven ability to set and meet own goals.Qualifications:M.S. or Ph.D. degree in Electrical or Computer engineering or in a physical science.Minimum of 10 years of experience working on digital logic design, standard cells benchmarking and test chip development in advanced nodes.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, AustinBusiness group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position.

For additional questions, please contact your Recruiter.Benefits:We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.

Find more information about all of our Amazing Benefits here: Annual Salary Range for jobs which could be performed in US, California:$180,270.00-$288,770.00Salary range dependent on a number of factors including location and experience.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

In certain circumstances the work model may change to accommodate business needs.SummaryLocation: US, Oregon, Hillsboro; US, California, Folsom; US, California, Santa Clara; US, Texas, Austin; US, Arizona, PhoenixType: Full time.